1. Field of the Invention
This invention relates to computers, and more particularly, to a setting/driving circuit for use in conjunction with an integrated circuit logic unit, such as a CPU having one or more multi-function pins. These pins provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins, to the CPU.
2. Description of Related Art
IBM-compatible personal computers (PC) are the most popular computer systems in the world. Earlier IBM-compatible PCs were constructed in compliance with the PC/XT and PC/AT standards. Since the IBM-compatible PCs are based on an open architecture, a great many various hardware technologies have been developed for use on them. For compatibility reasons, many new hardware technologies are integrated on the PC motherboard together with old ones. In addition, optional means, such as jumpers, are provided on the motherboard for the user to set parameters for the motherboard to operate in a user-desired manner.
The CPUs on the earliest PCs were only 4.77 MHz (megahertz) in speed, but today's high-end CPUs run at more than 400 MHz. When a new CPU is introduced, one problem encountered by this new CPU arises when it is mounted on a motherboard which is driven by a slower clock rate. In computer terminology, an internal clock rate refers to the clock rate actually used to drive the CPU, while an external clock rate refers to the clock rate used to drive the other circuit components on the motherboard. Present motherboards are typically 66 MHz or 100 MHz. Some motherboards use 75 MHz or 83 to MHz, but these are not standard types.
One solution to the problem of a high-speed CPU on a slow-speed motherboard is to multiply the motherboard clock rate to match the speed of the CPU. For instance, when a 400 MHz CPU is mounted on a 100 MHz motherboard, the 100 MHz clock rate from the motherboard is multiplied by 4 by an internal frequency multiplier in the CPU to obtain the desired 400 MHz clock rate; and when mounted on a 66 MHz motherboard, the multiplying factor is set to 6. The user can first determine the clock ratio of the internal clock rate of the CPU to the external clock rate from the motherboard by checking the specifications of the CPU and the motherboard, and then use switch means, such as jumpers, to set and input the clock ratio as parameter data to the CPU via certain pins on the CPU.
In IC manufacture, however, the total number of pins on a CPU is limited to a minimum for the purpose of making the CPU package more compact in size. Therefore, those pins that are used to receive the parameter data are typically also used for other I/O purposes after the CPU is set by the parameter data. Such pins are customarily referred to as multi-function pins. For instance, a multi-function pin may be used both for address signal output and for interrupt signal input. Typically, the parameter input to the CPU is carried out only during the initialization of the CPU; and after that, the multi-function pins used to receive the parameter data can be freed for other I/O functions during the remaining operation of the CPU.
FIG. 1 is a schematic diagram showing the use of a conventional setting/driving circuit in conjunction with a chip set 110 and a CPU 120 having a set of multi-function pins MA1, MA2, MA3, MA4. The CPU 120 also has a reset signal input pin RST (other I/O pins that are not related to the invention are not shown). The chip set 110 includes a control unit 112 having four output ports N1, N2, N3, N4 and a reset signal generator 114 having two output ports S and CPURST. The setting/driving circuit includes a set of switches 161, 162, 163, 164, such as jumpers; a set of resistors 171, 172, 173, 174; a selection circuit 130; a set of buffers 141, 142, 143, 144; and a set of resistors 151, 152, 153, 154. The selection circuit 130 has a first set of input pins A1, A2, A3, A4; a second set of input pins B1, B2, B3, B4; a set of output pins Y1, Y2, Y3, Y4; and a selection signal input pin SEL.
The chip set 110 and the CPU 120 are interconnected in such a manner that the RST input pin on the CPU 120 is connected to the CPURST output pin on the chip set 110. When the CPURST output pin is set at a low-voltage logic state, it causes the CPU 120 to be reset, whereas at a high-voltage logic state, causes the CPU 120 to operate normally. After the CPU 120 is reset, it reads the specified clock ratio setting via the multi-function pins MA1, MA2, MA3, MA4 during, for example, the first two cycles of the external clock rate from the motherboard. After this, the CPU 120 operates according to the settings to execute programs and switches the multi-function pins MA1, MA2, MA3, MA4 to a control data receiving mode to receive the control data, such as interrupt signals, from the control unit 112 in the chip set 110.
Further, a parameter setting means, which is composed of a set of switches 161, 162, 163, 164 and a set of resistors 171, 172, 173, 174, is coupled to the input pins A1, A2, A3, A4 of the selection circuit 130. The resistors 171, 172, 173, 174 each have a top end connected in common to the system voltage V.sub.CC and a bottom end connected to a corresponding one of the input pins A1, A2, A3, A4, while the switches 161, 162, 163, 164 each have a left end connected to the bottom end of the corresponding one of the resistors 171, 172, 173, 174 and a right end connected in common to the ground.
When any one of the switches 161, 162, 163, 164, for example the switch 161, is set to the conducting state (ON), it connects the corresponding input pin on the selection circuit 130, for example the input pin A1, to the ground, thereby setting that input pin to a low-voltage logic state, representing the input of a first logic value, for example 0, to the selection circuit 130. On the other hand, when set to a non-conducting state (OFF), it causes the corresponding input pin to be connected to the system voltage V.sub.CC, thereby setting that input pin to a high-voltage logic state, representing the input of a second logic value, for example 1, to the selection circuit 130. In total, there are 16 different ON/OFF combinations that can be set by the four switches 161, 162, 163, 164, and therefore 16 different clock ratio settings can be input via the selection circuit 130 to the CPU 120.
The chip set 110 contains all the control functions for the selection circuit 130 and the CPU 120. The control unit 112 and the reset signal generator 114 can be either integrated on the same IC chip or on two different IC chips, preferably on the same chip to save layout area on the motherboard. The chip set 110 and the selection circuit 130 are interconnected in such a manner that the output ports N1, N2, N3 N4 on the control unit 112 are connected respectively to the input pins B1, B2, B3, B4 on the selection circuit 130, and the output port S on the reset signal generator 114 is connected to the SEL input pin on the selection circuit 130. During normal operation of the CPU 120, the selection circuit 130 is set in such a manner as to connect the input pins B1, B2, B3, B4 to the output pins Y1, Y2, Y3, Y4 thereof, so as to allow the output control data, such as interrupt signals, from the control unit 112 to be transferred to the multi-function pins MA1, MA2, MA3, MA4 on the CPU 120.
The selection circuit 130 operates in such a manner that the output pins Y1, Y2, Y3, Y4 thereof are selectively connected to either the input pins A1, A2, A3, A4 or the input pins B1, B2, B3, B4 under the control of the voltage state (called the selection signal) at the SEL input pin received from the output port S of the reset signal generator 114 in the chip set 110. For instance, when the SEL input pin receives a low-voltage logic signal, it causes the selection circuit 130 to connect the output pins Y1, Y2, Y3, Y4 to the input pins A1, A2, A3, A4, thus allowing the parameter data set by the switches 161, 162, 163, 164 to be transferred to the multi-function pins MA1, MA2, MA3, MA4 on the CPU 120.
On the other hand, when a high-voltage logic signal is received, it causes the selection circuit 130 to connect the output pins Y1, Y2, Y3, Y4 to the input pins B1, B2, B3, B4, thus allowing the control data from the control unit 112 in the chip set 110 to be transferred to the multi-function pins MA1, MA2, MA3, MA4 on the CPU 120. In some cases, the chip set 110 and the CPU 120 may have different specifications in logic signal format. For instance the chip set 110 may be designed to handle logic signals between 0 V and 3.3 V, while the CPU 120 may be designed to handle logic signals between 0 V and 2.5 V. In this case, the first system voltage V.sub.CC in FIG. 1 is set to 3.3 V and the second system voltage V.sub.t is set to 2.5 V. The output logic signals from the output pins Y1, Y2, Y3, Y4 on the selection circuit 130, whether the parameter data from the switches 161, 162, 163, 164 or the control data from the control unit 112, are all encoded in 3.3 V format.
The purpose of the buffers 141, 142, 143, 144 and the resistors 151, 152, 153, 154 is therefore to convert the 3.3 V logic signals into 2.5 V format so that they can be handled by the CPU 120. The buffers 141, 142, 143, 144 are each of the type having an open-collector output characteristic that allows V.sub.t to be transferred to the multi-function pins MA1, MA2, MA3, MA4 when the input logic signals to the buffers 141, 142, 143, 144 are at the high-voltage logic state of 3.3 V, and 0 V to be transferred to the same when the input logic signals to the buffers 141, 142, 143, 144 are at the low-voltage logic state of 0 V.
As mentioned earlier, the CPU 120 needs to receive the specified clock ratio setting only during the initialization stage; and after that, the multi-function pins MA1, MA2, MA3, MA4 can be freed for other I/O functions all the time during the operation of the CPU 120. When the CPU 120 is reset, the reset signal generator 114 issues a reset signal from its CPURST output pin and then transfers this reset signal to the RST input pin on the CPU 120, and concurrently a selection signal is sent from its S output pin to the SEL input pin of the selection circuit 130.
FIG. 2 is a waveform diagram showing the timing relationships between the logic state at the CPURST output pin (the reset signal) and the logic state at the S output pin (the selection signal) of the reset signal generator 114. Normally, the CPURST and S output pins are both set at a high-voltage logic state. To reset the CPU 120, the reset signal generator 114 puts the CPURST output pin at the low-voltage logic state, and meanwhile also puts the S output pin also at low-voltage logic state.
The former condition resets the CPU 120 and also switches the multi-function pins MA1, MA2, MA3, MA4 to a parameter receiving mode, while the latter condition causes the selection circuit 130 to select and transfer the input data at the input pins A1, A2, A3, A4 (i.e., the parameter data from the switches 161, 162, 163, 164) from the output pins Y1, Y2, Y3, Y4 to the multi-function pins MA1, MA2, MA3, MA4 of the CPU 120. The parameter data are therefore input to the CPU 120 via the multi-function pins MA1, MA2, MA3, MA4. After this is completed, the voltage state at the CPURST output pin is switched back to high-voltage logic state, but the voltage state at the S output pin remains at the low-voltage logic state for a predetermined delay time DT to assure that the parameter data can be faithfully received by the CPU 120. The length of the delay time DT is dependent on the speed rating of the CPU 120.
In the case of a 400 MHz CPU, for example, the delay time DT is equal to two cycles of the external clock rate of the motherboard. At the end of the delay time DT, the voltage state at the S output pin is switched back to high-voltage logic state, which then causes the selection circuit 130 to select and transfer the input data at the input pins B1, B2, B3, B4 (i.e. the control data from the control unit 112) from the output pins Y1, Y2, Y3, Y4 to the multi-function pins MA1, MA2, MA3, MA4 of the CPU 120.
FIG. 3 is a schematic diagram showing a more detailed structure of the setting/driving circuit shown in FIG. 1, but the overall system is simplified to facilitate easy explanation of the operation of the setting/driving circuit. The CPU and the chip set shown in FIG. 1 are here designated respectively by the reference numerals 320 and 310, and the control unit and the reset signal generator included in the chip set 310 are respectively designated by the reference numerals 312 and 314. Although labeled with different reference numerals, these elements are functionally identical to those shown in FIG. 1. Since all the bits of the parameter data from the switches 161, 162, 163, 164 and the resistors 171, 172, 173, 174 shown in FIG. 1 are identical in operation, the simplified diagram of FIG. 3 shows only one switch and one resistor, as here designated respectively by the reference numerals 360, 370. Similarly, only one multi-function pin, designated by MA, is shown on the CPU 120, and only one buffer 340 and one resistor 350 are shown. Further, only one output pin A is shown on the control unit 312.
The selection circuit 130 shown in FIG. 1 can be realized by the combination of a first tri-state buffer 331, a second tri-state buffer 332, and an inverter 335 as shown in FIG. 3. The first tri-state buffer 331 has a gate GI connected via the inverter 335 to the S output pin on the reset signal generator 314 in the chip set 310, while the second tristate buffer 332 has a gate G2 connected directly to the same. The first tri-state buffer 331 operates in such a manner that when the gate G1 is set at a high-voltage logic state by the reset signal generator 314, it is enabled to cause its output to take on its input.
When at a low-voltage logic state, it is disabled to put its output at a high-impedance state (also called a floating state). The second tri-state buffer 332 operates in a similar manner. Therefore, when the reset signal generator 314 sets its S output pin at a high-voltage logic state, it causes the first tri-state buffer 331 to be disabled (since the logic state is inverted by the inverter 335) and the second tri-state buffer 332 to be enabled, thus allowing the second tri-state buffer 332 to transfer the control data from the output pin A of the control unit 312 via the buffer 350 to the multi-function pin MA of the CPU 320.
On the other hand, when the reset signal generator 314 sets its output pin S at a low-voltage logic state, it causes the first tri-state buffer 331 to be enabled (since the logic state is inverted by the inverter 335) and the second tri-state buffer 332 to be disabled, thus allowing the first tri-state buffer 331 to transfer the parameter data set by the switch 360 via the buffer 350 to the multi-function pin MA of the CPU 320.
One drawback to the foregoing setting/driving circuit, however, is that it is conventionally provided as a separate unit outside the chip set 110 since integrating it into the chip set 110 requires the chip set 110 to be provided with an increased number of pins, which would make the chip set 110 less compact in size. It is furthermore difficult and thus laborious to mount all the constituent elements of the setting/driving circuit as individual circuit components on the motherboard. The assembly of the setting/driving circuit on the motherboard is highly laborious and implementation requires a large layout area on the motherboard. The use of the conventional setting/driving circuit is therefore very cost-ineffective. There exists, therefore, a need in the computer industry for an improved setting/driving circuit that can help reduce the total number of IC units on the motherboard and also can help reduce the overall circuit complexity of the motherboard so as to allow easy and cost-effective implementation of the setting/driving circuit on the motherboard.